Modern electronic systems are placing ever-increasing demands on memory systems. As a result, the speed at which memory devices can communicate data is becoming increasingly important. The speed that memory devices can communicate data is often referred to as “memory bandwidth.”
Known methods for increasing memory bandwidth include increasing the operating frequency of the memory devices and increasing the number data lines to the memory device. Increasing the operating frequency is a challenge because timing margins become smaller and more difficult to manage. For example, the effects of clock skew and jitter become more pronounced as operating frequency is increased. Increasing the number of data lines requires a corresponding increase in the size of the external interface on the memory devices, as well as more physical traces on the circuit board that includes the memory devices. For a more in-depth discussion of these problems, see Richard Crisp et al., “Development of Single-Chip Multi-GB/s DRAMS,” IEEE International Solid-State Circuits Conference, Feb. 7, 1997.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for methods and apparatus to increase memory bandwidth.